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| ? ds3 payload access, bit-serial or nibble-parallel c-bit parity or m13 operating mode c-bit interface (13 c-bits in, 14 out) detect and generate ds3 ais, and idle signals transmit reference generator for serial operation transmit and receive far end alarm and control (feac) with double word capability and automatic transmission maskable hardware interrupt for eight alarms transmit single errors: framing, febe, c-bit parity, and p-bit parity febe, c-bit, and p-bit performance counters counters for f-bit and m-bit errors counter for coding violations and excessive zeros transmit-to-receive and receive-to-transmit loopbacks outputs can be set to high-impedance state selectable mode for txc-03401 emulation single +5 volt power supply available as 68-pin plastic leaded chip carrier or 80-pin thin plastic quad flat package (tqfp) the ds3f is designed for ds3 framer applications in which broadband payloads are mapped into the 44.736 mbit/s ds3 frame format. although the c-bit parity for- mat is recommended, the ds3f can also operate in the m13 mode. in the c-bit parity format, the ds3f provides a separate interface for selected c-bits. the ds3f also provides for transmitting and receiving the feac chan- nel and blue code ais conditions, and generates and detects ds3 ais, ds3 idle, p-bit parity and c-bit parity. in addition, performance counters are provided, as well as the ability to generate single framing, febe, c-bit parity and p-bit parity errors. the device also provides x-bit inversion, receive loop timing and indications for feac idle channel, feac word stack overflow and severely errored frame. the payload interface is select- able through software as either a bit-serial or nibble-par- allel format. subrate multiplexing wideband data or video transport ds3 monitor and test channel extenders ds3 test sets ds3f device ds3 framer TXC-03401B document number: TXC-03401B-mb ed. 6, june 2001 +5v serial/nibble tr a n s m i t d s 3 reference generator ds3 nrz i/o microprocessor ds3 stuff bits clock & data c-bits i/o clocks & data ds3f ds3 framer clock & data tr a n s m i t e r r o r s interface clock, data & frame output output serial/nibble clock, data & frame input line side terminal side TXC-03401B data sheet copyright ? 2001 transwitch corporation transwitch and txc and are registered trademarks of transwitch corporation proprietary transwitch corporation information for use solely by its customers applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com
- 2 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 table of contents section page list of figures ............................................................................................................... .....................2 block diagram ................................................................................................................. ..................3 block diagram description ..................................................................................................... ...........4 pin diagrams .................................................................................................................. ...................6 pin descriptions .............................................................................................................. ...................8 absolute maximum ratings and environmental limitations ............................................................17 thermal characteristics ....................................................................................................... ............17 power requirements ............................................................................................................ ...........17 input, output and input/output parameters ....................................................................................1 8 timing characteristics ........................................................................................................ .............20 operation ..................................................................................................................... ....................32 power, ground and external components ..............................................................................32 throughput delays ............................................................................................................. ......32 memory map .................................................................................................................... ................33 memory map descriptions ....................................................................................................... ........34 package information ........................................................................................................... .............45 ordering information .......................................................................................................... ..............47 related products .............................................................................................................. ...............47 standards documentation sources ............................................................................................... ..48 list of data sheet changes .................................................................................................... .........50 documentation update registration form* ................................................................................53 * please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com. customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. list of figures figure page 1 ds3f TXC-03401B block diagram .........................................................................................3 2 ds3f TXC-03401B 68-pin plcc pin diagram .......................................................................6 3 ds3f TXC-03401B 80-pin tqfp pin diagram .......................................................................7 4 line side ds3 receive input timing .....................................................................................20 5 line side ds3 transmit output timing .................................................................................21 6 terminal side receive nibble output timing ........................................................................21 7 terminal side transmit nibble input timing .........................................................................22 8 terminal side receive serial output timing .........................................................................23 9 terminal side transmit serial input timing ..........................................................................24 10 c-bit transmit input timing ................................................................................................. ..25 11 c-bit receive output timing ................................................................................................. 26 12 transmit reference generator timing ..................................................................................27 13 force error timing (c-bit parity, p-bit parity, febe) ............................................................28 14 force overhead bit error timing ...........................................................................................28 15 stuff opportunity bit timing (m13 mode) ..............................................................................29 16 microprocessor read cycle ..................................................................................................3 0 17 microprocessor write cycle .................................................................................................. .31 18 power supply connections ...................................................................................................3 2 19 ds3f TXC-03401B 68-pin plastic leaded chip carrier .......................................................45 20 ds3f TXC-03401B 80-pin thin profile plastic quad flat package ......................................46 - 3 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 block diagram figure 1. ds3f TXC-03401B block diagram crdcc crf crck crd x1 d3rd d3rc forcefebe forcepp /exzcnt forcecp /cvcnt d3td d3tc cxdcc cxf cxck cxd oena forceoe output p i/o transmit frame generator stufc stufd/hint rnib3 n.c. n.c. rds rcs rcg rfs rnib3 rnib2 rnib1 rnib0 rcn n.c. rfn sel rd wr ale ad(7-0) terminal side serial parallel line side n.c. xsc xck xfsi xds n.c. n.c. xfno xnc xck n.c. xnib3 xnib2 xnib1 input n.c. xnib0 reference fe x2 ds3 send ds3 interpreter ds3 frame alignment tdout tcg tfout tcout tfin tcin transmit receive rt payload loopback note: n.c. indicates no connection. - 4 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 block diagram description figure 1 shows the block diagram of the ds3f device. the ds3f is designed to operate in both "normal" (n) and "extended-features" (e) modes of operation. in the normal mode, the device emulates the transwitch txc-03401 ds3f device. in the extended-features mode, all the additional capabilities described in this data sheet are available. technical bulletin tb-511 describes the differences between the txc-03401 and the TXC-03401B (document number txc-03401-tb1). either mode of operation can be selected by setting control bit emode in the memory map. two input pins (forcecp /cvcnt and forcepp /exzcnt ) and one output pin (stufd/hint) can change their functions according to the mode selected (n/e). memory map addresses above 07h are effective only in the extended- features mode. the ds3f receives a line side ds3 data signal (d3rd) and a clock signal (d3rc) from a line interface device such as the transwitch art/arte vlsi device (txc-02020/02021) or ds3lim-sn module (txc-20153d or txc-20153g). the ds3 frame alignment block performs ds3 frame alignment that will not lock to a false framing pattern. there are internal 8-bit f- and m-bit error counters included in the extended-features mode of the framer to monitor errors. the ds3f also monitors the signal and the input clock for loss of signal (los), out of frame (oof), and loss of clock (loc). a framing error (fe) output is provided to indicate when any of the 31 framing bits in the ds3 signal are in error. the ds3 interpreter block performs p-bit and c-bit parity detection and error counting, receive ais and idle pattern detection, far end block error (febe) detection and error counting, far end alarm and control (feac) code word detection of up to 4 different types, c-bit reception and x-bit reception. serial interfaces are pro- vided for the received x-bits and for 14 of the 21 c-bits. in the extended-features mode, groups of the c-bits can be set by writing to the memory map. the receive c-bit interface consists of a serial data signal (crd), clock signal (crck), framing pulse (crf), and a data communication link clock signal (crdcc). the clock signal (crck) is gapped and is available only for clocking out c-bits c2 through c6, and c13 through c21. the crdcc clock signal is present only for c-bits c13, c14 and c15, which are assigned as a data communi- cation channel when operating in the c-bit parity mode. in the extended-features mode, the timing of the crdcc receive clock edges can be reversed by setting a control bit in the memory map. when operating in the m13 mode, an interface (output pin stufd) that indicates the state of the stuff opportu- nity bit during each of the seven ds3 subframes and a clock signal (stufc) are also provided. the stuff data status (stufd) output pin is shared with the hardware interrupt (hint) pin for the extended-features mode. the hardware interrupt output is used to the inform the microprocessor that a severe alarm condition has occurred. the polarity of the hardware interrupt output is selectable by a control bit to meet the requirements of the microprocessor's interrupt input pin. when a hardware interrupt does occur, it can be isolated to one of up to up to eight different latched alarm types if they are enabled in the memory map. the output block provides a bit-serial or a nibble-parallel interface for c-bit parity mode. the m13 mode uses the bit-serial interface only. note that since the sum of the payload and c-bits in a ds3 frame is not evenly divisible by four, m13 nibble mode operation is not feasible. the interface type is selected by writing to a control bit in the memory map (ser), and is common to the ds3f receive and transmit circuitry. the signals provided for the bit-serial interface consist of a data signal (rds), a clock signal (rcs), a receive clock gap signal (rcg ) and framing pulse (rfs ). the nibble-parallel interface consists of the nibble data signal (rnib3 through rnib0), a clock out signal (rcn), and a framing pulse output (rfn ). the rnib3 bit corresponds to the first bit received in a four-bit serial bit stream segment. in the transmit direction, the input block provides either a bit-serial or nibble-parallel interface. the bit-serial interface consists of a data signal (xds), clock signals (xck and optionally xsc), and a framing pulse (xfsi ). the nibble-parallel interface consists of the nibble data (xnib3 through xnib0), a clock out signal (xck), a framing pulse (xfno ), and a nibble clock signal (xnc). the xnib3 bit corresponds to the first bit transmitted. the ds3 send block performs p-bit and c-bit parity generation, ais and idle pattern generation, far end alarm and control (single or double feac word) transmission, x-bit insertion, and c-bit insertion. for c-bit parity - 5 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 mode, the c-bits may be generated internally (such as c-bit parity), written by the microprocessor (such as the feac channel), or provided from the external c-bit interface. in c-bit parity mode, the c1 bit is always trans- mitted as a 1. the transmit c-bit interface consists of a data input signal (cxd), a clock signal (cxck), a fram- ing pulse (cxf) and a data communication link clock (cxdcc). for m13 mode, all of the c-bits are input from the terminal side ? s bit-serial interface. the ds3 transmit line side interface consists of the data signal (d3td) and a clock signal (d3tc). ds3f transmit-to-receive (tr) loopback is controlled by setting a bit in the memory map (3loop). the entire device is used when loopback is in effect, but the line side input data and clock are blocked (by the gate pre- ceding the ds3 frame alignment block shown in figure 1). in the extended-features mode of operation, a receive-to-transmit payload (rtp) loopback is also available by use of control bit rtploop. the capability to generate and transmit single overhead bit errors is also provided. external interfaces are pro- vided for transmitting a far end block error (forcefebe ), a p-bit parity error (forcepp ), a c-bit parity error (forcecp ) and an overhead bit error (forceoe ). the forceoe signal is used in conjunction with the enable signal (oena) for introducing an overhead bit error in the next 85-bit segment of the ds3 frame. when the extended-features mode (emode), coding violation enable (cven) and excessive zeros enable (exzen) control bits in the memory map are set to 1, the coding violations count (cvcnt) function and excessive zeros count (exzcnt ) functions pin replace the forcecp and forcepp functions, respectively. the purpose of these pins is to utilize the ds3f's 16-bit counter cvexz to count coding violation and/or exces- sive zeros events. indications of these events are provided to the ds3f by transwitch's art or arte devices (txc-02020/02021). the art's cv output pin indicates both coding violations and excessive zeros. therefore, only the cvcnt input pin to the ds3f is required to count both types of event. when the arte is used in con- junction with the ds3f, there are separate cv and exz inputs available to the ds3f, which can be or-gated together in the ds3f's 16-bit counter, if required. the ds3f has an internal 16-bit shadow counter incorpo- rated into its counter design. this prevents cv or exz counts being lost during a read cycle. the transmit frame reference generator block provides reference timing for bit-serial operation. this block accepts an external 44.736mhz clock signal (tcin) and derives a clock signal (tcout), a framing pulse (tfout ), a clock gap signal (tcg ) and a data signal (tdout). the ds3 data signal consists of framing bits and zeros elsewhere. an optional input framing pulse (tfin ) is also provided, but is not required for normal operation. the ds3f microprocessor bus interface consists of eight bidirectional data and address pins (ad0-ad7), along with other microprocessor control pins. the microprocessor bus is used to write control information and to read status information and alarms. when operating in the extended-features mode the ds3f memory map contains twenty-one effective addresses (00h-14h), compared with eight (00h-07h) in the normal mode. when the ds3f is operating in the extended-features mode, its many additional features may be activated via control bits in the memory map. these features include: ability to tri-state all output ports, x-bit inversion, receive loop timing, receive and transmit blue code ais conditions, feac idle channel indication, a receive feac fifo stack overflow bit, a severely errored frame indication, and double feac word handling. - 6 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 pin diagrams figure 2. ds3f TXC-03401B 68-pin plcc pin diagram ale x1 rd x2 wr stufd/hint stufc vdd ad7 ad6 ad5 ad4 gnd ad3 ad2 ad1 ad0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 xnib0 xnib1 xnib2 forcecp /cvcnt xds/xnib3 forcepp/exzcnt forceoe gnd tcin vdd xfsi tfin tcout tfout tcg tdout gnd 60 59 58 57 56 55 54 53 52 51 50 49 48 46 45 47 oena sel test gnd d3rc vdd d3td xfno d3tc cxck gnd xsc/xnc cxf cxdcc vdd xck forcefebe 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 vdd cxd d3rd crdcc rfs /rfn rcg gnd rcs/rcn crf crck fe crd vdd rnib3 rnib2 rnib1 rds/rnib0 TXC-03401B 68-pin plcc (top view) ds3f please see figure 19 for package dimensions. - 7 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 3. ds3f TXC-03401B 80-pin tqfp pin diagram xsc/xnc forcefebe cxdcc gnd cxf d3rc xck sel vdd spare oena d3td spare spare gnd test vdd xfno d3tc cxck vdd d3rd spare spare cxd crdcc gnd rcs/rcn crf crck crd vdd rnib3 spare rnib2 rnib1 rds/rnib0 fe rfs/rfn rcg spare x1 spare spare ad7 ad2 ad0 ale ad1 rd wr stufd/hint stufc ad5 ad4 ad3 gnd ad6 vdd x2 spare tfin gnd tfout xfsi tcout xds/xnib3 tdout xnib1 tcg spare xnib0 forceoe spare spare forcecp /cvcnt xnib2 forcepp/exzcnt gnd tcin vdd 43 60 59 58 57 56 55 54 53 52 51 50 49 48 46 45 47 41 42 44 ds3f TXC-03401B 80-pin tqfp (top view) 11 12 13 14 15 16 17 18 19 20 9 8 7 6 5 4 3 2 1 10 23 40 39 38 37 36 35 34 33 32 31 30 29 28 26 25 27 21 22 24 67 66 65 64 72 62 63 73 80 61 68 69 70 71 74 75 76 77 78 79 32 please see figure 20 for package dimensions. - 8 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 pin descriptions power supply and ground *note: i = input; o = output; p = power ds3 receive line side interface * see input, output and input/output parameters section for type definitions . ds3 transmit line side interface symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p* type name/function vdd 4, 17, 27 38, 51, 63 1, 14, 30 44, 54, 70 p vdd: +5 volt supply voltage, 5% gnd 6, 22, 33 44, 53, 67 8, 21, 32 48, 57, 75 p ground: 0 volts reference. spare - 2, 9, 16, 22 29, 36, 42, 49, 56, 62, 69, 76 spare: these pins must not be connected to each other, to ground, or to any external circuit. connection could impair performance or cause damage. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type* name/function d3rc 5 55 i cmos ds3 receive clock: a 44.736 mhz clock used for clocking in receive data, and as the time base for the ds3f receiver. line side serial data is clocked into the ds3f on rising edges of the clock. d3rd 29 4 i ttl ds3 receive data: ds3 line side serial receive data. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function d3tc 1 51 o cmos 4ma ds3 transmit clock: a 44.736 mhz clock that is derived from the transmit clock (xck) signal and is used for clocking out the line side ds3 data sig- nal. data (d3td) is clocked out on rising edges of the clock. d3td 3 53 o cmos 4ma ds3 transmit data: ds3 line side serial transmit data. - 9 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 receive terminal side interface symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function rfs / rfn 31 6 o cmos 4ma receive framing pulse serial/nibble inter- face: the framing pulse is active low for one clock cycle (rcs/rcn), and is synchronous with the first bit 1 in the ds3 frame. for the nibble inter- face, the framing pulse is synchronous with nibble 1175. rcs/ rcn 34 10 o cmos 4ma receive clock serial/nibble interface: clock used for clocking out the terminal side receive serial and nibble data. this clock is derived from the line side clock (d3rc). data is clocked out of the ds3f on falling edges of the rcs clock and on rising edges of the rcn clock. rnib3 rnib2 rnib1 rds/ rnib0 39 40 41 42 15 17 18 19 o ttl 4ma receive nibble/serial interface: nibble data is clocked out on rising edges of the nibble clock (rcn). there are 1176 nibbles provided each frame. the data and clock are stretched to accommodate the 56 individual overhead bits (first bit in the 85-bit group), which are not pro- vided at the interface. the first bit received in a nibble is present on rnib3. the nibble interface is operational in the c-bit parity operating mode only. serial data (rds) consists of all the bits in the frame (including the states of the overhead bits), and is operational in either operating mode, m13 or c-bit parity. serial data is clocked out on falling edges of the receive clock (rcs). for serial data, a gapped clock signal is generated by the receive circuitry and provided on the rnib3 pin when control bits ser and rgcen are both set to 1. rcg 32 7 o cmos 4ma receive clock gap signal: the active low gap signal is synchronous with each overhead bit in the serial ds3 frame (first bit in the 85-bit group). - 10 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 transmit terminal side interface symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function xfno 2 52 o ttl 4ma transmit nibble interface framing pulse: an active low, one nibble clock cycle wide (xnc) pulse that occurs during the second nibble time. xfsi 50 28 i ttlp serial data transmit framing pulse: a framing pulse whose leading edge must be synchronous with bit 1 in the transmit serial data ds3 frame. the ds3f rewrites the 56 overhead bits based on the location of the transmit framing pulse. if this signal is held low for a duration greater than 1 frame, then all register bit positions at addresses 02h-04h, 05h bit 6 and 08h-14h (except 10h bit 6) will be reset to 0 until the pin is taken high. the xfsi pulse must not be applied while control bit rtploop is set to 1. xds/ xnib3 xnib2 xnib1 xnib0 56 58 59 60 35 38 39 40 i ttl transmit nibble/serial interface: nibble data is clocked in on rising edges of the nibble clock (xnc). there are 1176 nibbles in each frame. the clock is stretched to accommodate the 56 overhead bits which are not required at the inter- face. the ds3f inserts the x, f, c, p, and m over- head bits into the transmitted frame based on the framing pulse xfno . the first bit transmitted in a nibble is present on xnib3. the nibble interface is operational in the c-bit parity mode only. the serial data should consist of all the bits in the frame (4760 bits). the ds3f rewrites the 56 over- head bits in the frame based on the location of the framing pulse xfsi , when operating in the c-bit parity mode. in the m13 operating mode, the 21 c-bits are treated as user data, while the other overhead bits (x, f, p, and m bits) are written into the ds3 frame by the ds3f. serial data is clocked into the ds3f on rising edges of the transmit clock (xck). xck 62 43 i cmos transmit clock: provides the time base for the transmitter in the ds3f. in order to meet cross- connect objectives, the clock must operate at 44.736 mbit/s with a stability of 20 ppm and a duty cycle of (50 10)%. if xck fails, the ds3f uses the d3rc receive clock in its place. - 11 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 transmit reference generator interface xsc/ xnc 66 47 o cmos 4ma transmit nibble/serial clock: clock signal derived from the transmit reference generator clock (tcin). for nibble data, this clock (xnc) is stretched in order to accommodate the 56 over- head bit positions which are not required by the external terminal circuitry for the nibble interface (xnibn). for serial data, a gapped clock signal (xsc) is generated and provided on this pin when control bits ser and tgcen are both set to 1. this signal is synchronous with bit 1 in each 85- bit group (56 overhead bits) in the ds3 frame. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function tdout 45 23 o ttl 4ma transmit reference generator data output: ds3 frames are provided on this output that con- tain either all zeros or all ones. the number of frames with ones is 7 of every 18 frames. the pat- tern of the ones is one frame of every three for 15 frames and two of the last 3 of the 18-frame group; this completes the 7 of 18 pattern. the purpose of this pattern is to ease the require- ment to provide an all-ones and all-zeros c-bit pattern to insure a ds2 frequency that is very nearly equal to its specified value. tcg 46 24 o ttl 4ma transmit reference generator clock gap sig- nal: an active low, one clock cycle wide (tcout) signal that is synchronous with bit 1 in each 85-bit group (56 overhead bits) in the ds3 frame. tfout 47 25 o ttl 4ma transmit reference generator framing pulse: an active low, one clock cycle wide (tcout) pulse that is synchronous with bit 1 in the ds3 frame. may be used as the serial data transmit framing pulse (xfsi ) if properly delayed such that xfsi is aligned with an overhead-bit clock cycle. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function - 12 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 receive c-bit interface tcout 48 26 o cmos 4ma transmit reference generator clock out: clock signal that is derived from the transmit ref- erence generator clock input (tcin). provides a time base for multiplexing an external payload into the serial signal tdout provided by the refer- ence generator. may be used as the transmit input clock (xck) in the serial mode. transmit ref- erence generator signals are clocked out on rising edges of this clock. tcin 52 31 i ttl transmit reference generator clock in: pro- vides a time base for generating the various sig- nals in the ds3f transmit reference generator. in order to meet ds3 cross-connect objectives, this clock must operate at 44.736 mbit/s with a stabil- ity of 20 ppm and a duty cycle of (50 10)%. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function crdcc 30 5 o ttl 4ma c-bit receive data link clock: a gapped clock provided for clocking the three data link bits (c13, c14, and c15) into external circuitry from the serial data (crd). the rising edge of crdcc indi- cates when valid data is available. in extended mode, control bits are available to convert the three cycles into a single envelope pulse and/or to invert the signal ? s polarity (see figure 11). crf 35 11 o ttl 4ma c-bit receive framing pulse: provides a time base reference for clocking in the c-bits in a ds3 frame. crck 36 12 o ttl 4ma c-bit receive clock: a gapped clock which clocks c-bit data out of the ds3f. the falling edge of crck indicates when valid data is available. crd 37 13 o ttl 4ma c-bit receive data: serial interface for receiving the following c-bits in the c-bit parity mode: c2, c3, c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, and c21. availability of data is indicated by the clock signals crdcc and crck, described above. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function - 13 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 transmit c-bit interface other signals symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function cxd 28 3 i ttl c-bit transmit data: serial interface for transmit- ting the following c-bits in the c-bit parity mode: c2, c4, c5, c6, c13, c14, c15, c16, c17, c18, c19, c20, and c21. c-bit data is clocked into the ds3f on rising edges of the c-bit gapped clock (cxck). a c-bit must be transmitted as a one if not used. cxdcc 64 45 o ttl 4ma c-bit transmit data link clock: a gapped clock provided for clocking the three data link bits (c13, c14, and c15). in extended mode, a control bit is available to convert the three cycles into a single envelope pulse (see figure 10). cxf 65 46 o ttl 4ma c-bit transmit framing pulse: identifies the loca- tion of the first c-bit in the ds3 frame. cxck 68 50 o ttl 4ma c-bit transmit clock: a gapped clock which clocks the external c-bit serial data into the ds3f on rising edges. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function test 7 58 i ttlp transwitch test pin: leave open. oena 9 60 o ttl 4ma overhead enable: an active high signal that enables an overhead error to be introduced into the overhead bit in the next 85th group by placing a low on the forceoe pin. x1 11 63 o ttl 4ma ds3 received x-bit 1: an output indication of the state of the first x-bit received in the ds3 frame (bit 1). the indication is active until the next x1 state is detected. x2 13 65 o ttl 4ma ds3 received x-bit 2: an output indication of the state of the second x-bit received in the ds3 frame (bit 680). the indication is active until the next x2 state is detected. - 14 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 stufd/hint 15 67 o ttl 4ma stuff data status / hardware interrupt: in the nor- mal mode of operation (emode=0), this pin performs the stuff data status function. this output pin pro- vides an indication of the state of the stuff opportunity bit from the receive ds3 frame when operating in the m13 mode. for an m13 ds3 formatted signal, the first stuff opportunity bit occurs in the first bit after f4 (last 85-bit group) in subframe 1, and the last stuff opportu- nity bit in the frame occurs in the seventh bit after f4 (last 85-bit group) in subframe 7. in the extended-features mode of operation (emode=1), this output pin can be used (if hinten=1) to perform the hardware interrupt function. it may be used as input to the interrupt pin of the microprocessor. when at least one of the eight interrupt enable mask bits (address 11h, bits 7-0) is 1, occurrence of a corresponding alarm condition causes the pin to go high. this pin is used to inform the microprocessor that a severe alarm condition has occurred. the hardware interrupt signal may be changed to active low by setting control bit hintinv to 1. stufc 16 68 o ttl 4ma stuff clock: provided for clocking out the stuff oppor- tunity bit state. the rising edge occurs at the start of the second f-bit in a subframe and the falling edge occurs at the end of the fifth 85-bit group. fe 43 20 o ttl 4ma framing error indication: the fe pin will go high for every f-bit or m-bit framing error. it stays high for a period of 1.9 s (85 clock periods). during an out of frame condition the fe pin is held low. tfin 49 27 i ttlp transmit framing input: an optional active low input signal which resets the counters of the transmit frame reference generator block to zero and holds the output signals of the block to their corresponding states. forceoe 54 33 i ttlp force ds3 overhead bit error: an active low signal used in conjunction with the overhead enable signal (oena) for introducing an overhead bit error in the next transmitted 85-bit group. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function - 15 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 forcepp / exzcnt 55 34 i ttlp force p-bit parity error / excessive zeros count: in the normal mode of operation (emode=0), this pin performs the force ds3 p-bit parity error function. an active low signal generates and transmits a p-bit error by inverting both p-bits. if an active low signal is applied during the first subframe of the ds3 frame, the error is transmitted in that frame. otherwise the error is transmitted in the next frame. in the extended-features mode of operation (emode=1), this pin performs the excessive zeros count function when exzen=1. an internal 16-bit counter, cvexz at addresses 12h and 13h, is incre- mented when the pin is low during the rising edge of d3rc. this pin is intended to be driven by the exz excessive zeros output pin of the transwitch txc- 02021 arte device. forcecp / cvcnt 57 37 i ttlp force c-bit parity error / coding violation count: in the normal mode of operation (emode=0), this pin performs the force ds3 c-bit parity error function. an active low signal generates and transmits a c-bit parity error when operating in the c-bit parity mode. the error is transmitted by inverting c7, c8 and c9 (c-bit parity value) in subframe 3. if the active low sig- nal is applied during the first subframe of the ds3 frame, the error is transmitted in that frame. other- wise the error is transmitted in the next frame. in the extended-features mode of operation (emode=1), this pin performs the performs the cod- ing violation count function when cven=1. an inter- nal 16-bit counter, cvexz at addresses 12h and 13h, is incremented when the pin is high during the rising edge of d3rc. this pin is intended to be driven by the cv coding violation / excessive zeros output pin of the transwitch txc-02020 art device or the cv coding violation output pin of the transwitch txc-02021 arte device. forcefebe 61 41 i ttlp force febe error: an active low signal generates and transmits a far end block error (febe) when operating in the c-bit parity mode. if the active low signal is applied during the first subframe of the ds3 frame, the error is transmitted in that frame. other- wise the error is transmitted in the next frame. symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function - 16 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 microprocessor interface symbol 68-pin plcc pin no. 80-pin tqfp pin no. i/o/p type name/function sel 8 59 i ttl microprocessor select: a low enables the micro- processor to access the ds3f memory map for con- trol, status and alarm information. ale 10 61 i ttl address latch enable: an active high signal gener- ated by the microprocessor. used by the micropro- cessor to hold an address stable during a read/write bus cycle on the falling edge. rd 12 64 i ttl read: an active low signal generated by the micro- processor for reading the registers which reside in the ds3f memory map. the ds3f memory i/o is selected by placing a low on the select pin. wr 14 66 i ttl write: an active low signal generated by the micro- processor for writing to the registers which reside in the memory map. the ds3f memory i/o is selected by placing a low on the select pin. ad(7-4) ad(3-0) 18-21 23-26 71-74 77-80 i/o ttl 8ma address/data bus: these pins constitute the time multiplexed address and data bus for accessing the registers which reside in the ds3f memory map. - 17 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 absolute maximum ratings and environmental limitations notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the ? caution ? label on the drypack bag in which devices are supplied. 3. test method for esd per mil-std-883d method 3015.7. thermal characteristics power requirements parameter symbol min max unit conditions supply voltage v dd -0.3 +6.0 v note 1 dc input voltage v in -0.3 v dd + 0.3 v note 1 storage temperature range t s -55 150 o cnote 1 ambient operating temperature range t a -40 85 o c 0 ft/min linear airflow moisture exposure level me 5 level per eia/jedec jesd22-a112-a relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd absolute value 2000 v note 3 parameter min type max unit test conditions thermal resistance: junction to ambient for plcc 40 42 o c/w 0 ft/min linear airflow thermal resistance: junction to ambient for tqfp 48.3 50.7 o c/w 0 ft/min linear airflow parameter min type max unit test conditions v dd , supply voltage 4.75 5.0 5.25 v i dd , supply current 150 ma p dd , supply power 790 mw inputs switching - 18 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 input, output and input/output parameters input parameters for ttl input parameters for ttlp note: input has an internal pull-up resistor. input parameters for cmos output parameters for ttl4ma output parameters for cmos4ma parameter min type max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 5.5 pf parameter min type max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 0.2 ma v dd = 5.25; input = 0 volts input capacitance 5.5 pf parameter min type max unit test conditions v ih 3.15 v 4.75 < v dd < 5.25 v il 1.65 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 5.5 pf parameter min type max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -2.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 i ol 4.0 ma i oh -2.0 ma t rise 1.4 ns c load = 15 pf t fa l l 2.7 ns c load = 15 pf parameter min type max unit test conditions v oh v dd - 0.5 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 4.0 - 19 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 input/output parameters for ttl8ma i ol 4.0 ma i oh -4.0 ma t rise 1.9 ns c load = 15 pf t fa l l 2.0 ns c load = 15 pf parameter min type max unit test conditions v ih 2.0 v 4.75 < v dd < 5.25 v il 0.8 v 4.75 < v dd < 5.25 input leakage current 10 av dd = 5.25 input capacitance 5.5 pf v oh v dd - 0.5 v v dd = 4.75; i oh = -4.0 v ol 0.4 v v dd = 4.75; i ol = 8.0 i ol 8.0 ma i oh -4.0 ma t rise 1.3 ns c load = 25 pf t fa l l 2.5 ns c load = 25 pf parameter min type max unit test conditions - 20 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 timing characteristics detailed timing diagrams for the ds3f are illustrated in figures 3 through 16, with values of the timing intervals tabulated below each diagram. all output times are measured with a maximum 75 pf load capacitance. timing parameters are measured at voltage levels of (v ih + v il )/2 for input signals or (v oh + v ol )/2 for output signals. figure 4. line side ds3 receive input timing parameter symbol min type max unit d3rc clock period t cyc 20 22.35 ns d3rc high time t pwh 8.0 ns d3rc low time t pwl 8.0 ns d3rc duty cycle (t pwh /t cyc) -- 40 50 60 % d3rd set-up time to d3rc t su(1) 4.0 ns d3rd hold time after d3rc t h(1) 6.0 ns exzcnt set-up time to d3rc t su(2) 4.0 ns exzcnt hold time after d3rc t h(2) 6.0 ns cvcnt set-up time to d3rc t su(3) 4.0 ns cvcnt hold time after d3rc t h(3) 6.0 ns d3rc d3rd t cyc t pwh t pwl t su(1) t h(1) (input) (input) exzcnt (input) cvcnt (input) t su(2) t h(2) t su(3) t h(3) - 21 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 5. line side ds3 transmit output timing figure 6. terminal side receive nibble output timing parameter symbol min type max unit d3tc clock period t cyc 20 22.35 ns d3tc high time t pwh 8.0 ns d3tc low time t pwl 8.0 ns d3td output delay after d3tc t od 3.0 12 ns parameter symbol min type max unit rcn clock period t cyc 89 90.5 111 ns rcn high time t pwh 40 ns rcn low time t pwl 40 ns rnibn delay after rcn t od(1) 20 23 26 ns rfn delay after rcn t od(2) 20 23 26 ns rfn pulse width t pw 89 1 x t cyc 93 ns d3tc d3td t cyc t pwl t pwh t od (output) (output) rcn rnibn r fn t pw t od(2) t od(1) t cyc t pwh t pwl (output) (output) (output) nibble #1175 #1174 # 1176 # 1 nibble nibble nibble - 22 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 7. terminal side transmit nibble input timing note: xnib data input is latched at the midpoint of xnc low. parameter symbol min type max unit xnc clock cycle t cyc 89.0 90.5 111 ns xnc high time t pwh 40 63 ns xnc low time t pwl 40 50 ns xnibn set-up time to xnc t su(1) 26 ns xnibn hold time after xnc t h(1) -14 ns xfno output delay after xnc t od 0.0 2.0 8.0 ns xnc xnibn x fno n1 n2 n3 n4 t cyc t pwh t pwl n1176 t su(1) t h(1) t od (output) (input) (output) - 23 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 8. terminal side receive serial output timing parameter symbol min type max unit rcs clock period t cyc 20 22.35 ns rcs high time t pwh 8.0 ns rcs low time t pwl 8.0 ns rds, rcg , rfs output delay after rcs or rnib3 t od 0.0 2.5 5.0 ns 12345678 85 123 1234 123 one ds3 frame 1st 85-bit group bit 4760 rds rcs rfs rcg rds rcs rfs rcg t cyc t pwl t pwh t od (output) (output) (output) (output) rnib3* (output) (or rnib3*) * note: waveform generated when control bits ser and rgcen are both set to 1. the falling edge of rnib3 substitutes for rcs ? as a timing reference for rds, rcg and rfs . - 24 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 9. terminal side transmit serial input timing parameter symbol min type max unit xck clock period t cyc 20 22.35 ns xck high time t pwh 8.0 ns xck low time t pwl 8.0 ns xds set-up time to xck t su(1) 0.0 ns xds hold time after xck t h(1) 7.0 ns xfsi set-up time to xck t su(2) 2.0 ns xfsi hold time after xck t h(2) 5.0 ns one ds3 frame bit 4760 xds xck xfsi xds xck t pwl t su(1) t pwh t h(1) (input) (input) (input) t cyc 1 2 3 123 x fsi t su(2) t h(2) - 25 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 10. c-bit transmit input timing note: t cyc is the d3tc clock period (see figure 5). parameter symbol min type max unit cxck clock period t cyc(1) 170 x t cyc ns cxd set-up time to cxck t su 20 ns cxd hold time after cxck t h 40 ns cxck output delay after cxf t od 170 x t cyc ns cxf pulse width t pw 85 x t cyc ns c2 c4 c5 c6 c13 c14 c15 c16 c17 c18 c19 c20 c21 t od t pw t h cxd cxck cxdcc cxf (output) (input) (output) (output) t cyc(1) cxdcc (output if emode=1 and m13dlm=1) t su - 26 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 11. c-bit receive output timing note: t cyc is the rcs clock period (see figure 8). parameter symbol min type max unit crck clock period t cyc(1) 170 x t cyc ns crck output delay after crf t od(1) 170 x t cyc ns crd output delay after crck t od(2) 5.0 30 ns crf pulse width (high) t pw 85 x t cyc ns c2 c4 c5 c6 c13 c14 c15 c16 c17 c18 c19 c20 c21 t od(1) t pw crd crck crf t cyc(1) (output) (output) (output) (output) t od(2) c3 notes: 1. output for emode=0 or (emode=1, crdcinv=0 and m13dlm=0) 2. output for (emode=1, crdcinv=1 and m13dlm=0) 3. output for (emode=1, crdcinv=x and m13dlm=1) crdcc (output) crdcc see (output) crdcc see see note 1 note 2 note 3 - 27 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 12. transmit reference generator timing parameter symbol min type max unit tcin clock period t cyc(1) 20 22.3 ns tcin high time t pwh(1) 10 0.5 x t cyc(1) ns tcin low time t pwl(1) 10 0.5 x t cyc(1) ns tcin duty cycle (t pwh(1) /t cyc(1) ) -- 405060% tcout clock period t cyc(2) t cyc(1) 22.3 ns tcout high time t pwh(2) t pwh(1) 0.5 x t cyc(1) ns tcout output delay after tcin t od(1) 2.0 4.0 12 ns tdout output delay after tcout t od(2) 2.0 4.0 7.0 ns xsc output delay after tcin t od(3) 2.0 4.0 12 ns tfout output delay after tcout t od(4) 2.0 4.0 7.0 ns tcg output delay after tcout t od(5) 2.0 4.0 7.0 ns tfin set-up time before tcin t su 6.0 ns tfin hold time after tcin t h 2.0 ns tcin tcout tdout tfout tcg t cyc(1) t pwl(1) t pwh(1) t cyc(2) t od(1) t pwh(2) t od(2) framing pattern t od(4) t od(5) (input) (output) (output) (output) (output) * note: xsc signal occurs at pin 66/47 when control bits ser and tcgen are both set to 1. xsc * (output) t od(3) t h t su tfin (optional input) - 28 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 13. force error timing (c-bit parity, p-bit parity, febe) note: if the force error signal occurs during the first subframe of the ds3 frame (680 xck clock cycles), then the error occurs during that frame. otherwise, the error is transmitted in the next frame. figure 14. force overhead bit error timing note: forceoe resets oena. parameter symbol min type max unit force error wait time after framing pulse t w note ns force error low time t pwl 20 22 ns parameter symbol min type max unit d3tc clock period t cyc 20 22.35 ns oena output delay after d3tc t od(1) 0.0 7.0 ns oena pulse width (high) t pw(1) 9 x t cyc 80 x t cyc ns forceoe pulse width (low) t pw(2) 2 x t cyc 45 x t cyc ns oena delay from forceoe t od(2) 0.0 2 x t cyc ns xfsi t w t pwl (output) or xfno forcecp (input) forcepp for ce febe ohn 2 3 4 82 83 85 (output) d3tc (output) d3td (output) oena (input) forceoe 84 5 t od(1) t cyc t pw(2) t pw(1) t od(2) - 29 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 15. stuff opportunity bit timing (m13 mode) notes: 1. see figure 4 for timing of the d3rc and d3rd signals. 2. each block of 85 22.35 ns time slots is 1900 ns in duration. 3. the clock output stufc is intended to be used to strobe the data output stufd. it is a low frequency signal that repeats at 15.2 s intervals. stufd has a 3.8 s set up time to stufc and a hold time of 11.4 s after stufc . parameter symbol min type max unit d3rc clock period t cyc 22.35 ns stufc pulse width (high) t pw 3800 ns (input) d3rc (input) d3rd (output) stufc (output) stufd t pw (note gap at this point in each block) t cyc f41 284x 1 284f11 284c11 284f21 284c21 284f31 284c31 284f41 284x1284f11284 stuff bit, subframe 2 stuff bit, subframe 1 - 30 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 16. microprocessor read cycle notes: 1. the transmit clock (xck) or receive clock (d3rc) must be present for the microprocessor bus interface to operate. 2. a minimum of 10 clock cycles must occur after power-up, before the read cycles are valid. parameter symbol min type max unit ale pulse width t pw(1) 30 ns ale wait after rd t w(1) 0.0 ns address set-up time to ale t su(1) 20 ns address hold time after ale t h(1) 10 ns address hold time after rd t h(2) 50 ns data output delay (to tristate) after rd t od(1) 10 20 ns data output delay after rd t od(2) 80 ns sel wait after ale t w(2) 40 ns sel wait after rd t w(3) 40 ns rd pulse width t pw(2) 100 ns rd wait after ale t w(4) 10 ns t pw(1) t su(1) t w(1) t h(1) t w(4) t w(2) t pw(2) t od(2) ale ad(7-0) sel rd t h(2) t od(1) address data t w(3) - 31 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 figure 17. microprocessor write cycle notes: 1. the transmit clock (xck) or receive clock (d3rc) must be present for the microprocessor bus interface to operate. 2. a minimum of 10 clock cycles must occur after power-up, before the write cycles are valid. parameter symbol min type max unit ale pulse width t pw(1) 50 ns ale wait after wr t w(1) 0.0 ns address set-up time to ale t su(1) 30 ns address hold time after ale t h(1) 10 ns data set-up time to wr t su(2) 10 ns data hold time after wr t h(2) 20 ns sel wait after ale t w(2) 40 ns sel wait after wr t w(3) 70 ns wr pulse width t pw(2) 50 ns wr wait after ale t w(4) 10 ns t pw(1) t su(1) t w(1) t h(1) t w(4) t w(2) ale ad(7-0) sel wr t h(2) t pw(2) address data t w(3) t su(2) - 32 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 operation power, ground and external components figure 18. power supply connections figure 18 shows the recommended power and ground connection method for the ds3f device. separate planes should be employed for vdd and gnd. bypass networks consist of a 10 f capacitor in parallel with 0.1 f capacitors for each vdd pin, as shown. these 0.1 f capacitors should be rf-quality and closely con- nected to each of the device ? s vdd pins to decouple them to ground. throughput delays the ds3f throughput delays for the serial terminal interface are given below in terms of ds3 bit times (1 bit = 22.35 nsec nominal): 1. the throughput delay from the transmit terminal side input to the transmit line side output is 3 bit times. 2. the throughput delay from the receive line side input to the receive terminal side output is 2 bit times. TXC-03401B 4/1 17/14 27/30 38/44 51/54 6/8 22/21 33/32 44/48 53/57 67/75 note: all capacitors are 0.1 microfarads unless otherwise specified. vdd vdd vdd vdd vdd gnd gnd gnd gnd gnd gnd 10 f ds3f 63/70 vdd +5v + - 33 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 memory map note: at power-on, the memory map register contents are random and should be cleared by a register reset (see memory map descriptions section for addresses affected by the reset control bit at address 08h, bit 1). * note: r = read-only; r(l) = read-only, latched (clears on read); r/w = read/write. ** note: all unused read-only bits will contain 0. all unused read/write bits are to be set to 0 by the application software. *** note: addresses 08h through 14h are enabled only when control bit emode at address 05h, bit 7 is set to 1. address (hex) status* bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 r rxlos rxoof rxais rxidl rxloc txloc xrx2 xrx1 01 r/w nofebe txais enais txidl m13mode ser 3loop xtx 02 r febe / framing bit error performance counter (saturating counter, clears when read) 03 r c-bit parity error performance/number of frames counter (saturating counter, clears when read) 04 r p-bit parity error performance counter (saturating counter, clears when read) 05 r/w emode start feac transmit data 06 r fidl new feac receive data 07 r(l) rxlos rxoof rxais rxidl cerr loc x2err x1err 08 *** r/w fbec mbec tblue outdis itx2 itx1 reset lptime 09 *** r(l) sef unused** rblue unused** unused** unused** unused** stkovfl 0a *** r f-bit error counter (saturating counter, clears when read) 0b *** r m-bit error counter (saturating counter, clears when read) 0c *** r/w rtpllen rtploop testlock m13dlm dlcb1 c21 mcb1 cparinv 0d *** r/w ver dfexec double feac transmit data 0e *** r/w feac10 unused** rgcen tgcen hintinv hinten moofw crdcinv 0f *** r morefeac feacvlid rfeac6 rfeac5 rfeac4 rfeac3 rfeac2 rfeac1 10 *** r(l) rxlos rxoof rxais rxidl newfeac rtloc sef xerr 11 *** r/w rxlosen rxoofen rxaisen rxidlen nfeacien rtlocen sefen xerren 12 *** r coding violation / excessive zeros counter, low order byte (saturating counter, clears when read) 13 *** r coding violation / excessive zeros counter, high order byte (saturating counter, clears when read) 14 *** r/w stfren stftgen forcefebe forcepp forcecp tstcntr exzen cven - 34 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 memory map descriptions address bit symbol description 00 7 rxlos receive ds3 loss of signal: a receive los alarm occurs when the incoming ds3 data (d3rd) is stuck low for at least 2048 clock cycles (d3rc). recovery occurs when two or more ones are detected in the incoming data bit stream. 6 rxoof receive ds3 out of frame: a receive oof occurs when, in a sliding win- dow of 16 f-bits, three f-bits are in error, or when there are m-bit errors in two frames of a window of three (moofw=1) or four (moofw=0) consec- utive frames. recovery occurs when 16 consecutive error-free f-bits are detected in the repeating 1001 f-bit framing pattern, followed by the m-bit pattern of 010 being detected for two consecutive frames. recovery takes approximately 0.95 milliseconds, worst case. an oof also inhibits the per- formance counters at addresses 02h, 03h, 04h, 0ah and 0bh. the termi- nal output during an rxoof condition is the received data. 5rxais receive ds3 alarm indication signal (ais): a receive ds3 ais condi- tion is declared, and the rxais bit is set to 1, when rxoof is 0 and all of the following events have occurred during a frame: the three c-bits in each subframe have been 0 for five consecutive frames, at least 95% of the pay- load of each subframe has contained a repeating 1010.... bit sequence which begins after each overhead bit for five consecutive frames, and the latest x-bit received is the sixteenth or higher to have arrived with a 1 value in the most recent nineteen x-bits received (i.e., sixteen or more 1 values have occurred since there was an accumulated total of four 0 values). recovery to 0 occurs during the first subsequent subframe when one of these events could occur but does not. ais detection conforms to the bit error rate requirement stated in bellcore document tr-tsy-000191 (issue 1, may 1986), "alarm indication signal requirements and objectives." 4rxidl receive ds3 idle: a receive ds3 idle condition is declared, and the rxidl bit is set to 1, when rxoof is 0 and all of the following events have occurred during a frame: the c7, c8 and c9 bits in subframe 3 are 0, at least 95 per cent of the payload of each subframe contains a repeating 1100.... bit sequence which begins after each overhead bit for a period of one frame, and the latest x-bit received is the sixteenth or higher to have arrived with a 1 value in the most recent nineteen x-bits received (i.e., six- teen or more 1 values have occurred since there was an accumulated total of four 0 values). recovery to 0 occurs at the end of the first subsequent frame during which not all of these events occur. 3rxloc receive ds3 loss of clock: an alarm occurs when there are no transi- tions in the receive clock (d3rc) for seven or more xck clock cycles. xck clock must be present to count d3rc cycles. recovery occurs on the first transition of d3rc. 2txloc transmit ds3 loss of clock: an alarm occurs when there are no transi- tions in the transmit clock (xck) for seven or more d3rc receive clock cycles. d3rc clock must be present to count xck cycles. a failure causes the receive clock to become the transmit clock. this permits the micropro- cessor interface and transmitter to continue to function. recovery occurs on the first transition of xck. - 35 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 00 (cont.) 1xrx2 receive x-bit number 2: this bit position indicates the receive state of x2. this bit position is updated each frame. 0xrx1 receive x-bit number 1: this bit position indicates the receive state of x1. this bit position is updated each frame. 01 7 nofebe febe transmission disabled: a one written into this position disables the transmission of a febe when an f-bit or m-bit error or c-bit parity error occurs. 6txais* transmit ds3 alarm indication signal: a one written into this bit position causes the ds3f to transmit a ds3 ais. a one must also be written (if not already written) into bit 0 (xtx) in this register location in order to satisfy the definition of ds3 ais. txais is not effective when input pin xfsi is active low while operating with a bit-serial terminal side interface. 5enais enable transmit ds3 alarm indication signal automatically: a one written into this bit position causes the ds3f to transmit ds3 ais when the rxoof bit (register 00, bit 6) is set to 1. 4txidl* transmit ds3 idle signal: a one written into this bit position causes the ds3f to transmit a ds3 idle signal. a one must also be written (if not already written) into bit 0 (xtx) in this register location, in order to satisfy the definition of ds3 idle. 3m13mode m13 operating mode: a one enables the ds3f to operate in the m13 mode as specified in bellcore tr-tsy-000009, and the ansi t1.107-1995 standard. the m13 operating mode is available for the bit-serial terminal side interface only. a zero enables the ds3f to operate in the c-bit parity mode that is specified in the ansi t1.107-1995 standard. the c-bit oper- ating mode is available for either a serial or parallel terminal side interface. 2ser serial interface terminal side: a one configures the ds3f terminal side to be a serial interface for both receive and transmit. a zero configures the terminal side to be a nibble interface. the serial interface is operational in either the m13 or c-bit parity mode. the nibble interface is operational for the c-bit parity mode only. in the m13 operating mode, the transmit c-bit interface is disabled and terminal side c-bits are transmitted as user data. 13loop ds3 transmit-to-receive loopback: a one written into this bit position disables the receive input and causes the transmit output to be looped back as receive data. transmit data is provided at the output (d3td). 0xtx transmit x-bits: the x-bits may be used to transmit a yellow alarm or as a low-speed signaling channel. a one written into this bit position causes the ds3f to transmit a one for both x1 and x2. address bit symbol description - 36 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 02 7-0 fbn febe / framing bit error performance counter: this is a read-only 8- bit saturating counter that stops at a count of 255 and is automatically cleared to zero when it is read by the microprocessor. the integrity of the count is partially protected when the microprocessor reads the counter or the ds3f is in process of incrementing the counter. if an incoming count indication is received during one of these times, the indication is held and the counter is incremented once after completion of the read or increment cycle (i.e., any multiple indications received are recorded as a single incre- ment). when the ds3f is operating in the c-bit parity mode, this counter counts the febe indications received. a febe indication occurs for a received ds3 frame if any one or more of the c10, c11, or c12 bits in the frame is zero. when the ds3f is operating in the m13 mode, this counter counts framing bit error indications. an error indication occurs for each f-bit in a received ds3 frame that has a value different from the expected framing pattern. in the m13 mode, the counter is frozen during a ds3 loss of signal or an out of frame condition. 03 7-0 cpn c-bit parity error performance / number of frames counter: this is a read-only 8-bit saturating counter that stops at a count of 255 and is auto- matically cleared to zero when it is read by the microprocessor. the integ- rity of the count is partially protected when the microprocessor reads the counter or the ds3f is in process of incrementing the counter. if an incom- ing count indication is received during one of these times, the indication is held and the counter is incremented once after completion of the read or increment cycle (i.e., any multiple indications received are recorded as a single increment). when the ds3f is operating in the c-bit parity mode, this counter counts c-bit parity error indications. an error indication occurs for each received ds3 frame in which the majority (i.e., two or more) of the c7, c8 and c9 parity bits differ from the parity bit which was calculated by the ds3f over all 4704 received payload data bits of the preceding frame. for each such indication, the ds3f also provides a febe indication in the transmit line output, unless control bit nofebe is 1. when the ds3f is operating in the m13 mode, this counter counts ds3 frames. it takes approximately 27 milliseconds to count 255 frames. the application ? s software may use this ds3 frame count in conjunction with the count contained in the framing bit error counter (address 02h) to deter- mine an approximate bit error rate (ber). in the m13 mode, the counter is frozen during a ds3 loss of signal or an out of frame condition. address bit symbol description - 37 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 04 7-0 ppn p-bit parity error performance counter: this is a read-only 8-bit satu- rating counter that stops at a count of 255 and is automatically cleared to zero when it is read by the microprocessor. the integrity of the count is partially protected when the microprocessor reads the counter or the ds3f is in process of incrementing the counter. if an incoming count indi- cation is received during one of these times, the indication is held and the counter is incremented once after completion of the read or increment cycle (i.e., any multiple indications received are recorded as a single incre- ment). this counter counts p-bit parity error indications in either c-bit parity or m13 operating mode. an error indication occurs for each received ds3 frame during which one or both of the p1 and p2 bits differ from the parity bit calculated by the ds3f over all 4704 of the received payload data bits of the preceding ds3 frame. the ds3f does not provide a febe indica- tion in the transmit line output for each such indication. the counter is fro- zen during a ds3 loss of signal or an out of frame condition. 05 7 emode extended-features mode control bit: when this bit is set to 1, the extended-features mode of the ds3f is activated; control bit positions in memory map addresses above 07h are enabled. when this bit is set to 0, the normal mode of the ds3f is activated; control bit positions in memory map addresses above 07h are disabled. 6start start feac message: when start is set to 1, the ds3f starts to send repetitively the 16-bit feac code word, including the xxxxxx bits in bit positions 5-0, using the third c-bit (c3). if feac10 (address 0eh, bit 7) has been set to 1, the feac word is sent exactly 10 times and start is automatically reset to 0. if feac10 has been set to 0, the transmission of feac words is continuous until start is set back to 0, when the 16-bit code word is sent 10 more times before the message is terminated. the feac channel is then disabled and a 1 is subsequently sent in the third c- bit. (see also feac10 at address 0eh, bit 7.) 5-0 feac tr a n s m i t data transmit feac message: the third c-bit (c3) is used as a far end alarm and control (feac) channel. the feac channel uses a 16-bit code word that has the form 0xxxxxx0 11111111 to convey information, where the xxxxxx bits are the feac message. bit 0 corresponds to the right-most bit in the feac message. the feac word is inserted for the x ? s and the ds3f inserts the necessary 0 ? s and trailing 1 ? s to complete the 16-bit word. specific words that are transmitted for alarm or status conditions must be sent for the duration of the condition or a minimum of 10 code rep- etitions. when the feac channel is used for control purposes, the two- word control codes are repeated 10 times. for example, to activate or deactivate a loopback, the first loopback control code word must be trans- mitted 10 times, followed by 10 repetitions of the second ds3 (or ds1) line code word. (see also dfexec at address 0dh, bit 6.) address bit symbol description - 38 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 06 7 fidl receive single feac word: bit 7 (fidl) is the feac idle channel indica- tion. it clears whenever a zero c3 bit is received framing the six-bit variable word. bit 7 cannot be reset by a microprocessor read cycle. bit 6 (new) indicates when a new feac word has been detected. new is set when the ds3f receives a feac message for five consecutive feac message intervals (5 x 16 = 80 frames). it clears when the register is read. bits 5-0 (feac receive data) constitute the variable (xxxxxx) field in the feac word. a feac word is read in the field in the same order of being received as shown below: the following table lists possible feac combinations: note: there is no buffering for the received feac message. the latest, validated feac message is provided and bit 6 (new) is set to one even if the previous message is not read. 6new 5-0 feac receive data 07 7-0 rxlos rxoof rxais rxidl cerr loc x2err x1err latched-bit register: bits 7-4 in this location are the latched values of the corresponding bits in location 00h. all of the bits in this register latch and are cleared on a read cycle, but rxais maintains its value when the ds3f is in tr loopback or no tx terminal input is present. bit 3 (cerr) latches when the ds3f receives a c1 bit equal to zero. bit 2 (loc) latches when either an rxloc (bit 3 - 00h) or an txloc (bit 2 - 00h) occurs. the x2err and x1err bits (bits 1 and 0) are latched at the inverse of the xrx2 and xrx1 values (normally 1), so they are normally 0, and a value of 1 indicates an error in the corresponding received x-bit. address bit symbol description 16-bit feac word 1 1 1 1 1 1 1 1 0 0 x x x x x x x x x x x x bit 7 06h fidl new status 0 0 feac channel busy - no message received since last read cycle 1 0 feac channel idle - no message received since last read cycle 0 1 new message received - feac channel busy 1 1 new message received - feac channel idle - 39 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 08 7 fbec control f-bit error counter: when this bit is set to 1, the error counter in register 0ah will count only f-bit errors. when this bit is set to 0, the error counter will count both f-bit and m-bit errors. the integrity of the count is partially protected when the microprocessor reads the counter or the ds3f is in process of incrementing the counter. if an incoming count indi- cation is received during one of these times, the indication is held and the counter is incremented once after completion of the read or increment cycle (i.e., any multiple indications received are recorded as a single incre- ment). 6mbec control m-bit error counter: when this bit is set to 0, the error counter in register 0bh will count only m-bit errors. when this bit is set to 1, the error counter will count both m-bit and f-bit errors. the integrity of the count is partially protected when the microprocessor reads the counter or the ds3f is in process of incrementing the counter. if an incoming count indi- cation is received during one of these times, the indication is held and the counter is incremented once after completion of the read or increment cycle (i.e., any multiple indications received are recorded as a single incre- ment). 5tblue transmit blue code ais condition: when this bit is set to 1, the device will transmit all 1 ? s. 4 outdis output disable: when set to 1, this control bit disables all ds3f output pins except the microprocessor interface address/data bus. 3itx2 invert transmit x2: when set to 1, the x2 bit is inverted from the state specified by the xtx bit (address 01h, bit 0), which is 1 for xtx=1 and 0 for xtx=0. 2itx1 invert transmit x1: when set to 1, the x1 bit is inverted from the state specified by the xtx bit (address 01h, bit 0), which is 1 for xtx=1 and 0 for xtx=0. 1 reset reset: when set to 1, the transmit frame counter is reset. if left set to 1 for longer than one frame, then a register reset also occurs and this bit is cleared. when a register reset occurs, all bits in registers 02h - 04h and 08h - 14h, and bit 6 of register 05h, will be cleared. if this bit is set from 1 back to 0 before a frame has elapsed then no register reset will occur. if this bit is set to 1 when pin xfsi is low then a register reset occurs imme- diately. at power-on, the memory map register contents are random and reset should be used to clear to zero the bits it controls. 0lptime receive loop timing: when set to 1, this control bit disables the transmit clock input (xck) and causes the ds3 receive clock (d3rc) to become the ds3 transmit clock. xnc also becomes the ds3 receive clock. since the transmit reference generator does not switch to the ds3 receive clock, the lptime bit is invalid for serial mode applications. if the ds3 receive clock fails in this mode, the ds3f switches over to the transmit clock. address bit symbol description - 40 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 09 7 sef severely errored frame indication: a 1 indicates that a severely errored frame condition (sef) has been detected. an sef is defined as 3 out of 16 f-bits in error, utilizing a sliding window of 16 bits. this is a latched bit, and it clears on a microprocessor read cycle. this bit will then relatch if the condition that causes this bit to latch is still present. 6 unused this bit is internally set to 0. 5rblue receive blue code ais condition: when this bit is set to 1, the device has detected all 1 ? s. this is a latched bit, and it clears on a microprocessor read cycle. this bit will then relatch if the condition that causes this bit to latch is still present. 4-1 unused these four bits are internally set to 0. 0stkovfl stack overflow indicator for register ofh receive feac fifo: this bit is set to 1 when the receive feac circuit has detected and stored in its stack more than four feac words since the last read of register ofh. this is a latched bit, and it clears on a microprocessor read cycle. 0a 7-0 counter for errored ds3 f-bits (and m-bits): an 8-bit saturating counter that counts the number of f-bits that are in error since the last read cycle, if fbec at address 08h, bit 7 is set to 1. if fbec is set to 0, this counter will count both f-bit and m-bit errors. the counter is cleared on a microproces- sor read cycle. 0b 7-0 counter for errored ds3 m-bits (and f-bits): an 8-bit saturating counter that counts the number of m-bits that are in error since the last read cycle, if mbec at address 08h, bit 6 is set to 0. if mbec is set to 1, this counter will count both m-bit and f-bit errors. the counter is cleared on a micropro- cessor read cycle. 0c 7 rtpllen receive-to-transmit payload loopback lock enable: to activate receive-to-transmit payload loopback, this bit must first be set to 1 for at least one frame after rtploop (bit 6) has been set to 1 and then be set to 0. this resets the transmit frame counter so that the data will be synchro- nized to the overhead bits when using the loopback. the loopback com- mences on the transition to 0 and terminates when rtploop is cleared to 0. 6 rtploop receive-to-transmit payload loopback: this bit must be set to 1 to per- mit rtpllen (bit 7) to activate receive-to-transmit payload loopback. this loopback causes the receive output data (payload only) to be internally connected to the transmit side data input, as shown in figure 1. the loop- back condition is terminated by clearing this bit to 0. the xfsi input pulse must not be applied while rtploop is set to 1. 5testlock test lock: test bit to reset the transmit frame counter at a different time with respect to the receive. for test purposes only. normally set to 0. address bit symbol description - 41 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 0c (cont.) 4m13dlm m13 data link mode: when this control bit is set to 0, the c-bit transmit data link clocks (cxdcc and crdcc) are gapped clocks provided for clocking in the three data link bits (c13, c14, and c15). when set to 1, then the outputs cxdcc and crdcc become pulses that identify the location of the three data link c-bits (the same as in the m13 device). see figures 9 and 10. 3dlcb1 data link c-bits off: when set to 1, the c-bits used for the data link (c13, c14 and c15) will be set to 1. when set to 0, the values for these bits will be taken from the input pin cxd. 2c21 c2 off: when this bit is set to 1, the c2 bit will be 1. when this bit is set to 0, the c2 bit value will be taken from the input pin cxd. 1mcb1 most c-bits off: when set to 1, the c-bits c4 - c6, and c16 - c21 for the data link will all be set to 1. when set to 0, the data for these bits is taken from the input pin cxd. 0cparinv parity and febe c-bits off: when this control bit is set to 1, the c-bits used for parity (c7, c8, and c9) and the c-bits used for febe (c10, c11 and c12) will all be set to the inverse of the state that is calculated for the parity and febe. when set to 0, the data for these bits is taken from the calculations for parity and febe. 0d 7 ver version identifier: this is a read-only bit with a fixed value of 0. 6 dfexec execute double feac transmission: when set to 1, this control bit causes the ds3f to transmit 10 repetitions of the 16-bit feac codeword using data from the double feac transmit data field in bits 5-0, followed by 10 repetitions of the 16-bit feac codeword using data from the feac transmit data field in address 05h, bits 5-0. this bit is cleared upon com- pletion of the transmission. 5-0 double feac transmit feac message: the third c-bit (c3) is used as a far end alarm and control (feac) channel. the feac channel uses a 16- bit code word that has the form 0xxxxxx0 11111111 to convey informa- tion, where the xxxxxx bits are the feac message. bit 0 corresponds to the right-most bit in the feac message. the feac word is inserted for the x ? s and the ds3f inserts the necessary 0 ? s and trailing 1 ? s to complete the 16-bit word. specific words that are transmitted for alarm or status condi- tions must be sent for the duration of the condition or a minimum of 10 code repetitions. when the feac channel is used for control purposes, the two-word control codes are repeated 10 times. this field is used for the xxxxxx content of the first word of a double word message. both feac words are sent ten times automatically when dfexec is set to 1. address bit symbol description - 42 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 0e 7 feac10 transmit feac word 10 times: when set to 1, the duration of the single feac transmission (started by setting to 1 the control bit start in bit 6 of address 05h) is exactly 10 feac word times. the start bit is automati- cally reset to 0 at the end of the transmission. when set to 0, the single feac transmission is continuous. a continuous feac transmission cannot be terminated by setting this bit to 1. to terminate a continuous feac transmission, the start bit should be set to 0. (see also start at address 05h, bit 6.) 6 unused this bit is to be set to 0 by the application software. 5rgcen receive gapped clock output enable: when set to 1 while the ser (serial) bit is set to 1, a gapped clock signal is generated by the receive cir- cuitry and sent as output on the rnib3 pin (pin 39/15). 4tgcen timing generator gapped clock output enable: when set to 1 while the ser (serial) bit is set to 1, a gapped clock signal sent as output on the xsc/xnc pin (pin 66/47). this signal is synchronous with bit 1 in each 85- bit group (56 overhead bits) of the ds3 frame. 3hintinv hardware interrupt invert: when set to 1, this control bit inverts the hint output so that it becomes active low. 2hinten hardware interrupt enable: when set to 1, this control bit enables the stufd/hint output (pin 15/67) to generate a hardware interrupt to the microprocessor based on the existence of alarm conditions and the state of the interrupt mask register bits at address 11h. 1 moofw m-bit out of frame window: when set to 1, this control bit changes from 4 frames to 3 frames the duration of the window for m-bit errors that will cause the out of frame condition to be reported. 0 crdcinv crdcc extended-feature inversion: when set to 1 while control bit m13dlm=0, this control bit advances the timing of the three crdcc pulses by one-half a cycle of crck (see figure 11). 0f 7 morefeac more valid feac words remain in the stack: a 1 indicates that there is at least one more valid feac word in the stack (bits 5-0). 6feacvlid feac word valid: a 1 indicates that the feac word in bits 5-0 is valid. 5-0 rfeac6 rfeac1 receive feac stack: this field provides access to the top word of a four- word deep push-down fifo stack (maintained internally) that holds the received feac words. if more than four feac words have been received since the last read of this register then the stkovfl bit (address 09h, bit 0) will be set to 1. the stack will retain the 4 most recent feac words. address bit symbol description - 43 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 10 7 rxlos receive ds3 loss of signal interrupt: this latched bit is set to 1 when rxlos is detected. this bit is cleared when address 10h is read, but will then relatch if the condition that causes it to latch is still present. 6 rxoof receive ds3 out of frame interrupt: this latched bit is set to 1 when rxoof is detected. this bit is cleared when address 10h is read, but will then relatch if the condition that causes it to latch is still present. 5rxais receive ds3 alarm interrupt: this latched bit is set to 1 when rxais is detected. this bit is cleared when address 10h is read, but will then relatch if the condition that causes it to latch is still present. 4rxidl receive ds3 idle interrupt: this latched bit is set to 1 when rxidl is detected. this bit is cleared when address 10h is read, but will then relatch if the condition that causes it to latch is still present. 3newfeac new feac receive interrupt: this latched bit is set to 1 when a new feac word has been received 5 times consecutively. this bit is cleared when address 10h is read, but will then relatch if the condition that causes it to latch is still present. 2rtloc receive or transmit ds3 clock failure interrupt: this latched bit is set to 1 when either rxloc or txloc occurs. this bit is cleared when address 10h is read, but will then relatch if the condition that causes it to latch is still present. 1sef severely errored frame indication interrupt: this latched bit is set to 1 when sef occurs. this bit is cleared when address 10h is read, but will then relatch if the condition that causes it to latch is still present. 0xerr receive x-bit error interrupt: this latched bit is set to 1 when x1 or x2 is 0. this bit is cleared when address 10h is read, but it will relatch if a condi- tion that causes it to latch is still present. 11 7 rxlosen alarm interrupt enable mask bits: if any of the eight bits in this register is set to 1, a hardware interrupt will be generated at the stufd/hint out- put pin (pin 15/67) when the corresponding latched alarm bit is set to 1 in the register at address 10h, provided that the hinten bit at address 0eh, bit 2 is set to 1. 6 rxoofen 5rxaisen 4rxidlen 3nfeacien 2rtlocen 1sefen 0xerren address bit symbol description - 44 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 12 7-0 cvexz7- cvexz0 coding violation 16-bit counter, low order byte: a 16-bit saturating counter that counts the d3rc cycles for which cvcnt is high (and those for which exzcnt is low, if exzen is set to 1). these signals are outputs from the art (cv only) and arte devices and they are expected to be related to the rising edge of d3rc. there are actually two counters, so that when one counter is being read, the other counter is counting. a read cycle for this register causes this switch to toggle, and the current count data for the low order byte to be provided as output. note: the counter switch will toggle whenever ale goes low while this address is selected, so care should be taken if multiple ds3f devices are on the proc. i/o bus. 13 7-0 cvexz15- cvexz8 coding violation 16-bit counter, high order byte: a read cycle for this register causes the high order count byte which corresponds to the most recently read low order count byte from the register at address 12h to be provided as output and then this counter (all 16 bits) is cleared to 0000h. it is therefore important to read the register at address 12h first, followed by a read of this register, to insure that a correct count is obtained. 14 7 stfren stuff receive enable: when set to 1, the rcg output of the receive data circuitry will include the stuff bit locations if 2 out of 3 c-bits in that sub- frame are set to 1, when operating in m13 mode and serial mode. 6 stftgen stuff timing generator enable: when set to 1, the tcg output of the timing generator will include the stuff bit locations when operating in m13 mode and serial mode. 5 forcefebe force febe error: when the cven bit is set to 1, setting this bit to 1 will generate and transmit a far end block error (febe) by setting c10, c11, c12 to 0 in the next available ds3 frame when operating in the c-bit parity mode. to send an additional error, the microprocessor must first set this bit to 0 before again setting it to 1. 4 forcepp force p-bit parity error: when the cven bit is set to 1, setting this bit to 1 will generate and transmit a p-bit error by inverting both p-bits in the next available ds3 frame. to send an additional error, the microprocessor must first set this bit to 0 before again setting it to 1. 3 forcecp force c-bit parity error: when the cven bit is set to 1, setting this bit to 1 will generate and transmit a c-bit parity error (c7, c8 and c9 inverted) in the next available ds3 frame when operating in the c-bit parity mode. to send an additional error, the microprocessor must first set this bit to 0 before again setting it to 1. 2 tstcntr test counter: this bit should be set to 0. 1exzen excessive zeros enable: when set to 1, the exz events are counted in the cvexz counter. 0cven coding violation counter enable: setting this bit to 1 disables the forcecp , forcepp and forcefebe input pins from performing their original force error functions and allows these functions to be performed instead by setting to 1 bits 3, 4 and 5 of this register. the forcecp input pin is then defined as the cvcnt (coding violation) input pin and the forcepp input pin as the exzcnt (excessive zeros) input pin to the cvexz 16-bit counter in the registers at addresses 12h and 13h. address bit symbol description - 45 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 package information the ds3f device is packaged in a 68-pin plastic leaded chip carrier (plcc) suitable for socket or surface mounting, as shown in figure 19, or as an 80-pin thin profile plastic quad flat package suitable for surface mounting, as shown in figure 20. figure 19. ds3f TXC-03401B 68-pin plastic leaded chip carrier 0.954 sq. 0.800 sq. top view bottom view 0.990 sq. 0.200 transwitch 961 27 43 10 26 60 44 1 9 61 27 43 10 26 60 44 1 0.075 0.050 typ. 0.017 typ. note: all dimensions are shown in inches and are nominal unless otherwise indicated. max. min. 0.020 TXC-03401Bipl - 46 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 the ds3f device is also available as an 80-pin thin profile plastic quad flat package suitable for surface mounting, as illustrated in figure 20 (the plcc version is shown in figure 19). figure 20. ds3f TXC-03401B 80-pin thin profile plastic quad flat package 60 41 21 20 1 80 pin #1 index 9.50 typ 12.00 14.00 1.70 (max) 0.05 (min) 1.40 typ see detail ? a ? 0.50 typ 0.14 (min) 0.26 (max) detail ? b ? detail ? c ? see details ? b ? and ? c ? 0.30 (min) 0 o - 10 o detail ? a ? 12.00 14.00 9.50 typ 0.127 typ 0.70 (max) note: all linear dimensions are in millimeters and are nominal unless otherwise indicated. 40 61 transwitch TXC-03401Bitq - 47 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 ordering information part number: TXC-03401Bipl 68-pin plastic leaded chip carrier part number: TXC-03401Bitq 80-pin thin plastic quad flat package related products txc-02020 (02021), art (arte) vlsi device (advanced ds3/sts-1 receiver/transmitter). performs the receive and transmit line interface functions required for transmission of ds3 (44.736 mbit/s) or sts-1 (51.840 mbit/s) signals across a coaxial interface. the arte is an extended-feature version of the art, in a larger package. txc-02030, dart vlsi device (advanced e3/ds3 receiver/transmitter). dart performs the transmit and receive line interface functions required for transmission of e3 (34.368 mbit/s) and ds3 (44.736 mbit/s) signals across a coaxial interface. txc-03303, m13e vlsi device (ds3/ds1 mux/demux, extended features). this single- chip multiplex/demultiplex device provides the complete interfacing function between a single ds3 signal and 28 independent ds1 signals. txc-03305, m13x vlsi device (ds3/ds1 mux/demux). this single-chip device provides the functions needed to multiplex and demultiplex 28 independent ds1 signals to and from a ds3 signal with either an m13 or c-bit frame format. it includes some enhanced features rel- ative to the m13e device. txc-03452b, l3m vlsi device (level 3 mapper). the l3m maps a e3/ds3 line signal into a stm-1 tug-3 or sts-3/sts-1 spe or sts-1 spe sdh/sonet signal. txc-03453, tl3m vlsi device (triple level 3 mapper). the tl3m maps up to 3 indepen- dent e3/ds3 line signals into an stm-1 tug-3 or sts-3 sts-1 spe sdh/sonet signal. txc-06125, xbert vlsi device (bit error rate generator/receiver). programmable multi- rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability. txc-21005, ds3f/xbert evaluation board. a complete, ready-to-use test system that demonstrates the functions and features of the ds3f vlsi device. includes on-board micro- processor, rs-232 interface, xbert, and ms-dos compatible pc software for control and monitor. - 48 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 11 west 42nd street fax: (212) 302-1286 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 2570 west el camino real tel: (650) 949-6700 suite 304 fax: (650) 949-6705 mountain view, ca 94040 web: www.atmforum.com atm forum europe office av. de tervueren 402 tel: 2 761 66 77 1150 brussels fax: 2 761 66 79 belgium atm forum asia-pacific office hamamatsu-cho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsu-cho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt ( see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (314) 726-0444 (outside u.s.a.) 7730 carondelet avenue, suite 407 fax: (314) 726-6418 clayton, mo 63105-3329 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 22 650 route des lucioles fax: 4 92 94 43 33 06921 sophia antipolis cedex web: www.etsi.org france - 49 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (508) 650-1375 washington, dc 20007 web: www.mvip.org itu-t (international): publication services of international telecommunication union tel: 22 730 5111 telecommunication standardization sector fax: 22 733 7256 place des nations, ch 1211 web: www.itu.int geneve 20, switzerland mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 building 4 / section d fax: (215) 697-1462 700 robbins avenue web: www.dodssp.daps.mil philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 2575 ne kathryn street #17 tel: (503) 693-6232 (outside u.s.a.) hillsboro, or 97124 fax: (503) 693-8344 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-core (within u.s.a.) attention - customer service tel: (908) 699-5800 (outside u.s.a.) 8 corporate place fax: (908) 336-2559 piscataway, nj 08854 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunications technology committee tel: 3 3432 1551 fax: 3 3432 1553 2nd floor, hamamatsu-cho suzuki building, web: www.ttc.or.jp 1 2-11, hamamatsu-cho, minato-ku, tokyo - 50 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 list of data sheet changes this change list identifies those areas within this updated ds3f data sheet that have significant differences relative to the previous and now superseded ds3f TXC-03401B data sheet: updated ds3f data sheet: edition 6, june 2001 previous ds3f data sheet: edition 5, march 1998 the page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. 1 added 80-pin tqfp package option to last feature bullet item. 2 updated table of contents and list of figures for effects of adding figures 3 and 20, and adding the tqfp pin column to the tables in the pin descrip- tions section. added second sentence to the note. 3 added arrow from transmit frame reference generator block to input block in figure 1. 7 changed title of figure 2 and added figure 3, 80-pin tqfp pin diagram. 8-16 added 80-pin tqfp pin no. column in pin descriptions tables. added spare pins on page 8 for tqfp. 11 changed description for symbol xsc/xnc to state that clock signal is der- vived from tcin. 17 in first table, deleted component temperature x time row and modified esd row, adding note 3. in second table, added thermal characteristics for tqfp package. 27 in table of figure 12, added max time for symbol t od(3) . 31 in figure 17, added symbol t su(2) and clarified t w(2) . changed min value for symbol t w(3) in table. 33 added note at beginning of memory map descriptions section. 39 added last sentence to description for symbol reset. 41 deleted description for symbol ver after first sentence. 27, 32, 42, 43 added location of corresponding pin on tqfp package to existing location of pin on plcc package in note about xsc signal in figure 12, for vdd and gnd leads in figure 18, and in description columns for symbols rgcen, tgcen, hinten and address 11h. 44 added note to description for symbols cvexz7-cvexz0. 46 added figure 20 to provide tqfp to package information. 47 added 80-pin tqfp package option to ordering information section. 47 changed related products section. 48 replaced standards documentation sources section. 50 replaced list of data sheet changes section. - 51 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. - 52 of 54 - transwitch corporation ? 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 - 53 of 54 - ds3f TXC-03401B data sheet proprietary transwitch corporation information for use solely by its customers TXC-03401B-mb ed. 6, june 2001 documentation update registration form if you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the marketing communications department at transwitch. marketing communications will ensure that the relevant product information sheets, data sheets, application notes, technical bulletins and other publications are sent to you. you may also choose to provide the same information by fax (203.926.9453) , or by e-mail (info@txc.com) , or by telephone (203.929.8810) . most of these documents will also be made immediately available for direct download as adobe pdf files from the transwitch world wide web site ( www.transwitch.com ). name: ________________________________________________________________________________ company: ___________________________________________ title: ______________________________ dept./mailstop: __________________________________________________________________________ street: ________________________________________________________________________________ city/state/zip: __________________________________________________________________________ if located outside u.s.a., please add - country: _______________ postal code: ___________________ telephone: ________________________ ext.: _____________ fax: __________________________ e-mail: ________________________________________________ please provide the following details for the managers in charge of the following departments at your company location. department title name company/division __________________ __________________ engineering __________________ __________________ marketing __________________ __________________ please describe briefly your intended application(s) and indicate whether you would like to have a transwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ if you are also interested in receiving updated documentation for other transwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ please fold, tape and mail this page (see other side) or fax it to marketing communications at 203.926.9453. please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this transwitch product as it becomes available. (fold back on this line first.) (fold back on this line second, then tape closed, stamp and mail.) transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 3 enterprise drive shelton, ct 06484-4694 u.s.a. transwitch corporation attention: marketing communications dept. 3 enterprise drive shelton, ct 06484-4694 u.s.a. first class postage required |
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